The present invention relates, in general, to electronics and, more particularly, to integrators and methods to integrate signals.
In the past, the electronics industry used active circuits to perform signal integration. The active circuits consumed significant power and introduced noise components into the integrated signal. Typically the active circuit included an operational amplifier in a closed loop negative feedback configuration. FIG. 1 is a circuit schematic of a prior art integrator 10. What is shown in FIG. 1 is an operational amplifier 12 in a negative feedback configuration. Operational amplifier 12 has a noninverting input terminal coupled for receiving a reference voltage VREF1 and an inverting input terminal connected to a capacitor 14, which is coupled for receiving an input signal VIN through a switch 16. In addition, the inverting input terminal is connected to an output terminal 26 of operational amplifier 12 through a switch 18 and through a switch 20 and a capacitor 22. Switches 16 and 18 have control terminals that are coupled for receiving a control signal VSW1 and switch 20 has a control terminal coupled for receiving a control signal VSW2. Switch 16 and capacitor 14 have terminals that are commonly connected together and to a terminal of a switch 24. In addition, switch 24 has a terminal coupled for receiving a reference voltage VREF2 and a control terminal coupled for receiving a control signal VSW3.
A load capacitor 28 is coupled between output terminal 26 and a source of operating potential VSS.
The operation of integrator 10 is explained with reference to timing diagram 40 illustrated in FIG. 2. At time t0, control voltages VSW1, VSW2, and VSW3 are at logic low voltage levels and output voltage VOUT is at voltage level VREF1. A reset and sampling phase is initiated by applying a voltage VSW2 at the control terminal of switch 20 at time t1 and a voltage VSW1 at the control terminals of switches 16 and 18 at time t2. More particularly, voltages VSW2 and VSW1 transition from a logic low voltage level to a logic high voltage level at times t1 and t2, respectively. In response to the logic high voltage, switches 16, 18, and 20 close, operational amplifier 12 enters a unity gain operating mode, and the voltages at the inverting and noninverting input terminals equal reference voltage VREF1. Capacitor 14 samples input voltage VIN and is charged to a level Q14S. Because integrator 10 is in a unity gain configuration, capacitor 22 is shorted and as a consequence no charge is accumulated. At time t3, control signal VSW1 transitions to a logic low voltage level ending the sampling period for capacitor 14.
In response to control signal VSW3 transitioning to a logic high voltage level at time t4, switch 24 closes coupling reference voltage VREF2 to capacitor 14 and beginning the integration phase. Output voltage VOUT increases from voltage level VREF1 to a voltage level VINT1. The output voltage VOUT1 after one integration step may be given by Equation 1 (EQT 1):VOUT1−(VREF1)−(C14/C22)*(VIN−VREF2)   EQT 1
where:
C14 is the capacitance value of capacitor 14; and
C22 is the capacitance value of capacitor 22.
At time t5, control voltages VSW2 and VSW3 transition to a logic low voltage level, opening switches 20 and 24, respectively, and maintaining the charge on capacitor 22.
Another sampling step begins at time t6, at which time control signal VSW1 transitions to a logic high voltage level and ends at time t7 at which time control signal VSW1 transitions to a logic low voltage level. At time t8 control signal VSW2 transitions to a logic high voltage level beginning another integration phase. At time t9 control signal VSW3 transitions to a logic high voltage level and output voltage VOUT transitions from voltage level VREF1 reaching voltage level V INT2 at time t10. In addition, control signal VSW3 transitions to a logic low voltage level at time t10 and control signal VSW2 transitions to a logic low voltage level at time t11. Thus, FIG. 2 illustrates two integration steps. For N integration steps, where N is an integer, the output voltage VOUTN can be given by Equation 2 (EQT 2):VOUTN−(VREF1)−N*(C14/C22)*(VIN−VREF2)   EQT 2
A drawback with the integrator architecture of FIG. 1 is that it needs an operational amplifier consisting of multiple active elements that are in continuous operation which increases power consumption and introduces noise components.
Accordingly, it would be advantageous to have an integrator and a method for performing integration with reduced power consumption and improved noise performance. It is desirable for the integrator and method to be cost and time efficient to implement.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or an anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten per cent (10%) (and up to twenty per cent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.
It should be noted that a logic zero voltage level (VL) is also referred to as a logic low voltage or logic low voltage level and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic zero voltage may be thirty percent of the power supply voltage level. In a five volt Transistor-Transistor Logic (TTL) system a logic zero voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (VH) is also referred to as a logic high voltage level, a logic high voltage, or a logic one voltage and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.